As shown in FIG. 8, a semiconductor logic circuit is shipped through three stages, which are designing, manufacture and testing stages. In the testing stage, a test vector, wherein the logic value of each logic bit is determined as either 0 or 1, is applied to the manufactured semiconductor logic circuit, and a test response from the semiconductor logic circuit is observed and compared to an expected test response, so that it is judged if the circuit is defective or non-defective. A ratio by which the non-defective products can be obtained is called yield, and the yield largely affects the quality, reliability and manufacturing costs of the semiconductor logic circuit.
In general, the manufactured semiconductor logic circuit is mostly a sequential circuit. The sequential circuit comprises a combinational circuit unit including one or a plurality of AND gates, one or a plurality of NAND gates, one or a plurality of OR gates, one or a plurality of NOR gates and the like, and flip-flops for memorizing internal states of the circuit. Hereupon, the combinational circuit unit comprises an external input pin (primary input: PI), a pseudo external input pin (pseudo primary input: PPI) which is an output pin of the flip-flop, an external output pin (primary output: PO), and a pseudo external output pin (pseudo primary output: PPO) which is an input pin of the flip-flop. Inputs to the combinational circuit unit include those directly supplied from the primary input and those supplied via the pseudo primary input. Outputs from the combinational circuit unit include those appearing on the primary output directly and those appearing on the pseudo primary output.
In order to test the combinational circuit unit of the sequential circuit, it is necessary to apply a required test vector from the primary input and the pseudo primary input of the combinational circuit unit and observe a test response from the primary output and the pseudo primary output of the combinational circuit unit. Bits corresponding to the primary input and the pseudo primary input constitute one test vector, and bits corresponding to the primary output and the pseudo primary output constitute one test response.
However, in general, the output pin (pseudo external input pin) and the input pin (pseudo external output pin) of the flip-flop of the sequential circuit cannot be directly accessed from outside. Therefore, there are problems in the controllability of the pseudo primary input and the observability of the pseudo primary output when the combinational circuit unit is tested.
A method of solving the problems described above in the controllability and observability in the test of the combinational circuit unit which is mostly adopted is the full-scan design. Describing the full-scan design, the flip-flops are replaced with scan flip-flops, and the scan flip-flops are used to form one or a plurality of scan chains. The operation of the scan flip-flops is controlled by a scan enable (SE) signal pin. For example, when SE=0, the operation of the scan flip-flops is the same as that of the conventional flip-flops, and output values of the scan flip-flops are updated by a value from the combinational circuit unit when a clock pulse is given thereto. When SE=1, the scan flip-flop and another scan flip-flop in the same scan chain form one shift register, and new values are shifted into the scan flip-flops from outside and current values in the scan flip-flops are shifted out therefrom when the clock pulse is given thereto. The scan flop-flops in the same scan chain conventionally share the same scan enable (SE) signal pin, however, the scan flop-flips in the different scan chains may share the same scan enable (SE) signal pin or may respectively use different ones.
The combinational circuit unit of the full-scan sequential circuit is tested in such a manner that scan shift and scan capture are repeated. The scan shift is performed in shift mode wherein the scan enable (SE) signal pin is set to logic value 1. In the shift mode, one or a plurality of clock pulses is given, and one or a plurality of new values is shifted into the scan flip-flops in the scan chain from outside, and, at the same time, one or a plurality of current values in the scan flip-flops in the scan chain is shifted out therefrom. The scan capture is performed in capture mode wherein the scan enable (SE) signal pin is set to logic value 0. In the capture mode, one clock pulse is simultaneously given to all of the scan flip-flops in one scan chain, and a value of the pseudo primary output in the combinational circuit unit is captured into all of the scan flip-flops.
The scan shift is used in order to apply the test vector to the combinational circuit unit via the pseudo primary input and observe the test response from the combinational circuit unit via the pseudo primary output. Further, the scan capture is used to capture the test response from the combinational circuit unit into the scan flip-flops. All of the test vectors are subjected to the scan shift and the scan capture so that the combinational circuit unit can be tested. Such a test method is called the scan test method.
In the scan test method, the test vector may be applied to the combinational circuit unit directly via the external input or by means of the scan shift. Because an arbitrary logic value can be set in an arbitrary scan flip-flop by the scan shift, the problem in the controllability of the pseudo primary input can be solved. The observation of the test response from the combinational circuit unit may be performed directly via the external output or by means of the scan shift. Because the output value of the arbitrary scan flip-flop can be observed by means of the scan shift, the problem in the observability of the pseudo primary output can be solved. As described, it is only required in the scan test method to obtain the test vector and the expected test response using an automatic test pattern generation (ATPG) program.
The scan test method described above, which is a very effective means, still includes the problem that more power is consumed in the test than in a normal operation. In the case where a CMOS circuit constitutes a semiconductor logic circuit, the power consumption includes static power consumption due to leak current and dynamic power consumption due to the switching activity of logic gates and flip-flops. Further, the latter power consumption, which is the dynamic power consumption, includes shift power consumption in a shift operation and capture power consumption in a capture operation.
A large number of clock pulses are conventionally given to one test vector at the time of the scan shift. For example, it is necessary to supply as many clock pulses as the number of the scan flip-flops at maximum in order to set new values in all of the scan flip-flops in one scan chain. Therefore, the shift power consumption is thereby increased, which may cause excessive heat. The excessive heat may lead to the breakage of the semiconductor logic circuit. Therefore, a method of reducing the shift power consumption has been actively studied.
The number of the clock pulses necessary for one test vector at the time of the scan capture is conventionally one for one scan chain. Therefore, the heat resulting from the scan capture power consumption does not present any problem. However, if there is a difference between the test response value and the current value of the scan flip-flop when the test response of the combinational circuit unit appearing on the pseudo primary output is captured into the scan flip-flop in the capture mode, the output value of the corresponding scan flip-flop changes. In the case where there is a large number of scan flip-flops which thus change the output values, a power supply voltage tentatively drops due to the switching activity of the logic gates and the scan flip-flops, which is called the IR (I: current, R: resistance) drop. The IR-drop may result the malfunction of the circuit, as a result of which a wrong test value may be captured into the scan flip-flop. Accordingly, the semiconductor logic circuit normally operable in a normal operation, may be wrongly judged to be a defective product when tested. As a result, the yield is deteriorated. In the case where the semiconductor logic circuit achieves a large scale, ultra-miniaturization and lower power supply voltage, the yield loss induced by the false test is evident. Therefore, it is necessary to reduce the capture power consumption.
In the case where a single clock is used in the test, the scan capture power consumption can be reduced by means of the clock gating method, which, however, largely affects the physical design of the semiconductor logic circuit. In the case where a multiple clock signal is used in the test, the scan capture power consumption can be reduced by means of the one-hot method or multiple clock method. However, a test data volume is significantly increased in the first, while an enormous amount of memory consumption is necessary for the generation of the test vector in the latter, which both impose a significant burden on the ATPG. In the process of reducing the scan capture power consumption, it is desirable to minimize the influence on the physical design, the increase of the test data volume and the burden on the ATPG.
A test cube including don't care bits, that is, a logic bit which can be either the logic value 0 or the logic value 1 for achieving a predetermined object, is often generated in the process where the test vector is generated according to the ATPG program. In contrast, a test input not including the don't care bits but only includes logic bits (bits having the logic value 0 or logic value 1) is called a test vector. In the case where a test vector set not including the don't care bits is supplied, a part of the bits of a part of the test vectors can be set as the don't care bits without any change to a fault coverage of the set. In other words, the test cube can be obtained by a don't care bit specified program. The test cube is present because one or a plurality of target faults in the combinational circuit unit of the full-scan sequential circuit can be often detected when the necessary logic values are simply set in a part of the bits in the primary input and the pseudo primary input. Though 0 or 1 is set in the rest of the bits, the target faults are still detected. Therefore, such bits unrelated to the detection are the don't care bits for the target faults.
By the way, X-filling is the process of assigning logic values to the unspecified bits (X-bits) in a test cube so as to obtain a fully-specified test vector with a certain characteristic. Because of no need of circuit modification or ATPG algorism modification, X-filling is evaluated to be acceptable for capture power reduction. X-filling methods for capture power reduction are different from random X-filling. And they can be collectively called LCP (Low-Capture-Power) X-filling. As shown in Non-Patent Document 1, 2, 3 and 4, LCP X-filling methods are proposed as new X-filling methods. In addition to no circuit/ATPG impact, one more important advantage of LCP X-filling is its compatibility with any shift power reduction solution that is not based on the use of X-bits. As a result, total (shift and capture) test power reduction can be achieved.
FIG. 9 shows an example of using MD-SCAN (multi-duty scan) (Refer to Non-Patent Document 5) for shift power reduction and LCP X-filling for capture power reduction.
MD-SCAN lowers shift power by using multiple shift clock phases to reduce the number of simultaneously-operating FFs. It cannot reduce capture power, however, since only one capture clock phase is used in order to contain ATPG complexity and memory usage. Nonetheless, since MD-SCAN does not rely on X-bits, LCP X-filling can use the X-bits to generate test vectors with low capture power. This leads to a complete solution for total scan test power reduction. In many cases, capture power reduction is more critical than shift power reduction. For example, in the case shown in FIG. 9, shift power can be readily reduced to 1/n if n shift clock phases are used. However, if capture power is not sufficiently reduced, the goal of total scan test power reduction cannot be achieved. Therefore, it is highly required to reduce capture power as effective as possible.    Non-Patent Document 1: K. M. Butler, J. Saxena, T Fryars, G. Hetherington, A. Jain, and J. Levis, “Minimizing Power Consumption in Scan testing: Pattern Generation and DFT Techniques,” Proc. Intl. Test Conf., pp. 355-364, 2004.    Non-Patent Document 2: R. Sankaralingam, R. Oruganti and N. Touba, “Static Compaction Techniques to Control Scan Vector Power Dissipation,” Proc. of VLSI Test Symp., pp. 35-42, 2000.    Non-Patent Document 3: X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita, “Low-Capture-Power Test Generation for Scan-Based At-Speed Testing,” Proc. Intl. Test Conf., Paper 39-2, 2005.    Non-Patent Document 4: X. Wen, H. Yamashita, S, Kajihara, L.-T. Wang, K. Saluja, and K. Kinoshita, “On Low-Capture-Power Test Generation for Scan testing,” Proc. VLSI Test Symp., pp. 265-270, 2005.    Non-Patent Document 5: T. Yoshida and M. Watari, “A New Approach for Low Power Scan testing,” Proc. Intl. Test Conf., pp. 480-487, 2003.